Filling high aspect ratio isolation structures with polysilazane based material

ABSTRACT

Isolation trenches and capacitor trenches containing vertical FETs (or any prior levels p-n junctions or dissimilar material interfaces) having an aspect ratio up to 60 are filled with a process comprising: applying a spin-on material based on silazane and having a low molecular weight; pre-baking the applied material in an oxygen ambient at a temperature below about 450 deg C.; converting the stress in the material by heating at an intermediate temperature between 450 deg C. and 800 deg C. in an H20 ambient; and heating again at an elevated temperature in an O2 ambient, resulting in a material that is stable up to 1000 deg C., has a compressive stress that may be tuned by variation of the process parameters, has an etch rate comparable to oxide dielectric formed by HDP techniques, and is durable enough to withstand CMP polishing.

BACKGROUND OF INVENTION

The field of the invention is that of filling high aspect ratio trenchesin integrated circuit processing.

As ground rule dimensions shrink in integrated circuits, the problem offilling high aspect ratio trenches increases, in particular forisolation trenches used in the shallow trench isolation process, STI,that is commonly used in advanced processing.

The industry-standard filling material and process has been siliconoxide, SiO2, deposited with the high density plasma, HDP, technique.This method has been widely adopted because it produces a high qualitymaterial that has good filling properties. Designers of integratedcircuits have adapted their structural and material specifications tothis process and material.

Since silicon is piezo-electric, the properties of field effecttransistors, FETs, are affected by the stress on the transistor convertsthe stress in the material from tensile to compressive.

Another aspect of the invention is a stress conversion step followed byan anneal in a dry ambient.

Another aspect of the invention is a first heating step in a steamambient followed by the anneal in a dry ambient.

Another aspect of the invention is the ability to relate total alloweddevice temperature budget and the annealing step to tune the stress andwet etch rate of the final material.

BRIEF DESCRIPTION OF DRAWINGS

FIGS. 1A-1C illustrate a portion of a substrate in the course of theinvention.

FIGS. 2A, 2B illustrate an optional step of applying an HDP cap layer.

FIG. 3 illustrates the filling of an aperture with a reentrant profile.

FIG. 4 shows a graph of material stress resulting from differenttreatments.

FIG. 5 shows a graph of relative etch rates resulting from differenttreatments.

FIG. 6 shows a graph of relative etch rates resulting from differenttreatments.

FIG. 7 shows a graph of material composition resulting from differenttreatments.

DETAILED DESCRIPTION

The basic sequence in an SOD application is illustrated in FIG. 1, inwhich a silicon substrate 10 having a pad nitride/oxide 20 has a set ofapertures that have been etched in it by any convenient process, e.g. areactive ion etch. Two sizes of apertures are shown to illustrate thatactual wafers will have a variety of values for the spacing betweenapertures and the width of the apertures, as well as different depths.The variation may result from fluctuations in a single etching processthat may depend, for example, on the pattern density or it may resultfrom the simultaneous filling of apertures formed in two differentprocesses.

On the right of FIG. 1A, aperture 34 has a width 48 and a depth 46,giving an aspect ratio of 46/48. Apertures 32 have a width 44 and adepth 42, giving an aspect ratio 42/44. It is evident that the aspectratio of the apertures 32 will be higher than that of aperture 34, sothat the process in question will need to accommodate a range of aspectratios.

In the course of the process, a trench dielectric material fillingsubstance, referred to as a spin-on dielectric (SOD) or spin-on glass(SOG) will be applied to the wafer, which is rotated to spread thematerial quite uniformly over the surface. The material, which has asuitably low viscosity, will penetrate into the various apertures andoverfill, with a top surface 52 above the top surface of pad 20. Theresult is shown in FIG. 1B.

The wafer is then planarized by CMP or by an etchback step to remove theexcess overfill material, as shown in FIG. 1C.

FIG. 1C also shows an extra thickness of oxide 57 formed along the sidesof the apertures by annealing the material in an oxidizing ambient. Aconventional step of annealing in an ambient containing water vaporconverts the Nitrogen and Hydrogen in the silazane to ammonia andmolecular Hydrogen that escapes from the material, leaving a residuethat is largely silicon oxide. The presence of oxygen in the ambientassists in converting Si—N bonds to Si—O bonds. The properties of thefinal material will depend on the degree to which this conversion hasbeen accomplished.

FIGS. 2A and 2B illustrate an optional aspect of the invention, in whichthe silazane fill 54 is recessed by any conventional etch and a caplayer 62 of HDP is deposited by standard techniques and planarized withCMP.

Those skilled in the art will appreciate that the process will be moreconsistent and the results better if the stress of the silazane layer 54is close to that of HDP layer 62.

Spin-on materials have the well known property that they fill variousaperture profiles that a process such as chemical vapor depositioncannot fill. Referring now to FIG. 3, there is illustrated an aperture310 having a reentrant profile, meaning that there is at least one levelwhere the transverse dimension B is less than the correspondingtransverse dimension A at or near the top of the aperture. This occursby design in the case of a trench capacitor or by accident when a divothas been formed on a wall that is intended to be smooth.

FIG. 3C illustrates the result of a CVD application, with a void 325that has been formed in the body of material 320′. In contrast, FIG. 3Bshows the result of a spin-on application that fills the apertureuniformly.

It is well known in the art that the industry standard material forisolation trenches, referred to as shallow trench isolation, or STI, isHigh Density Plasma-assisted oxide (HDP oxide), which will not fillapertures uniformly when the aspect ratio is more than about 4 (assuminga vertical trench sidewall profile).

In modern processing, there is very strong pressure to increase thedensity of features on a chip, so that the aspect ratio is constantlyincreasing. Process engineers are now working on filling trenches withaspect ratios in the range of about 10 and planning on filling trencheswith much higher aspect ratios.

Various complex and expensive schemes are in use to fill high aspectratio trenches that involve depositing a portion of the total material,cleaning out the upper portion of the aperture so that new material isnot blocked, then filling a second portion, etc.

Process engineers go to this effort in spite of the much better fillingproperties of spin-on materials because no spin-on material is currentlyacceptable. In the case of isolation trenches, it is not enough that thefilled trench insulate—i.e. not conduct current. Process integrationrequires that the steps in the process and the properties of theresulting material must be consistent with the rest of the process andstructure.

Since the processes in use at the present time have been developed to beconsistent with the properties of HDP oxide, it would require a greatdeal of effort to alter those current processes. It would be highlyadvantageous if a spin-on process could be developed that would emulatethe material properties of the HDP material.

The inventors have realized that it is possible to tune the stress,composition and wet etch resistance of a spin-on material to be similarto those of HDP oxide.

Poly-silazane processed according to the manufacturer's recommendationsproduces a final material that has properties very different from thoseof HDP, having poor etch resistance, tensile stress and low density.

According to the invention, the sequence of processing steps is:

Spin-on silazane having a molecular weight in the range of 2000-4000dissolved in a solvent such as dibutyl ether;

Pre-bake in O2 ambient (400-700 Torr) at a temperature in the range100-450 deg C. for a period of 20-120 min;

Perform a first anneal in water vapor at a temperature in the range450-800 deg C. for a period of 20-120 min;

In case temperature budget of prior levels allows: Perform a secondanneal in an oxygen ambient without water vapor (400-700 Torr) at atemperature between 800-1200 deg C. for a period of 20 -120 min.

Planarize the resulting film by CMP.

For deep STI trenches (aspect ratio>6), an additional step is an extraanneal in water vapor at a temperature in the range 450-800 deg C. for aperiod of 20-120 min after CMP to ensure that material at the bottom ofthe trench is oxidized and converted from Si—N bonding to Si—O bonding.

It is an advantageous feature of the invention that the parameters ofthe final product can be varied by varying the processing parameters.Illustratively, the final material is high quality oxide with lowimpurity contamination; has a wet etch removal ratio (WERR) at 900 degC. of less than 1.5; has compressive film stress in the range of 0.1 to2 Gdyne/cm2; can be planarized by CMP with a standard slurry; isthermally stable at temperatures greater than 1000 deg C.; and hasthickness uniformity (<1% sigma) superior to HDP oxide.

Referring now to FIG. 4, the graph shows the material stress in asilazane film annealed with steam and with oxygen ambients. Point 410shows a typical value for HDP oxide. Curve 420 shows the result of asteam anneal between 700 and 900 deg C. As can be seen, the points at800 deg C. and 900 deg C. are quite close to HDP, while the result offilms annealed in an oxygen ambient (curve 430) have a tensile stress.

FIG. 5 shows corresponding curves for the wet etch rate ratio i.e. theratio of the etch rate of the film in question to the rate of thermaloxide. The etch material is buffered hydrofluoric acid (BHF). Theresults, on curve 520, of the steam anneal at 800 and 900 deg C. areagain very similar to the results of HDP oxide, point 510, while theresults of the oxygen anneal, curve 530, are much higher (having lessetch resistance).

FIG. 6 shows corresponding results for the refractive index of theresulting oxide. The refractive index is a measure of material densityas well as silicon to oxygen stoichometric ratio.

Again, curve 620 (the steam anneal) is closer to point 610, typical ofHDP oxide, while the points on curve 630, the oxygen anneal, areconsiderably different.

FIG. 7 shows the composition of films after anneals at two differenttemperatures (in steam). The residual concentration of C (curve C), N(curve NSi) and hydrogen (Curve H) are much higher at 700 deg C. than at1000 deg C.

While very high temperature steam anneal (1000 C) produces the film withlow impurity levels it is obviously can not be used if prior levelsjunctions have lower temperature budget restrictions. In the case of avertical transistor, the STI is often done after the transistor has beenformed and for example any prolonged (>10 min) anneal above 900 C isprohibited assuming 100 nm vertical DRAM groundrule.

Another well known issue with high temperature steam oxidation ofsilicon is the formation of defects which decrease activation energy fordopant diffusion (such as B, P, As, etc) and subsequent increase intheir diffusion coefficients (so called oxygen enhanced diffusion(OED)). This effect in turn causes even bigger unwanted changes in priorp-n junction profiles.

It has been also found, that steam oxidation above a temperature of 800deg C. produces excessive oxidation of the silicon in the wafer (eitherbulk, epitaxial or SOI) that can degrade the parameters of thetransistor that will be formed in the active area. Thick oxide film(>300 A) grows on an STI sidewall (especially the top corner portion)and creates stress in adjacent active areas as well as increases thenumber of defects. Defects are easily formed in the top STI corner,after pad SiN strip and subsequent etch and anneal processing steps. Thestress in the active areas may vary according to the circuit design.What is beneficially provided by the present invention is that the newtrench material does not change the stress that the transistor wasdesigned for.

Once a silazane film is subjected to a first 800 C steam anneal it isbeneficial to proceed with a second anneal in oxygen at temperatures>800C. Such an anneal further decreases the wet etch rate ratio (to about1.1 of that of thermal oxide) and keeps film stress compressive withinthe range of 0.5-2 Gdyne/cm2.

The properties of the final film can be adjusted or tuned by varying thetime of the steam anneal and of the oxygen anneal.

While the invention has been described in terms of a single preferredembodiment, those skilled in the art will recognize that the inventioncan be practiced in various versions within the spirit and scope of thefollowing claims.

1. A method of forming an integrated circuit containing a set ofthermally sensitive circuit elements having a thermal budget associatedtherewith and a set of isolation trenches comprising the steps of:providing a silicon substrate; forming at least one circuit elementhaving a thermal budget prior to forming the isolation structure;etching said set of trenches in said silicon substrate; filling said setof trenches with a spin on trench dielectric material containingsilazane; heating said substrate at a temperature of less than about 450deg C.; converting the stress in said trench dielectric material fromtensile stress to compressive stress by heating in an ambient containingH2O at a temperature between about 450 deg C. and about 900 deg C.;annealing said substrate by heating in an ambient containing O2 at atemperature above 800 deg C.; and completing said integrated circuit. 2.A method according to claim 1, in which the time of the stressconversion step and the time of the anneal step are related such thatthe thermal budget of the thermally sensitive component is not exceeded.3. A method according to claim 1, in which: said step of stressconversion and said step of annealing are related such that theresulting material has compressive stress in the range of 0.1 to 2Gdynes/cm2 and has a WERR of less than about
 2. 4. A method according toclaim 2, in which: said step of stress conversion and said step ofannealing are related such that the resulting material has compressivestress in the range of 0.1 to 2 Gdynes/cm2 and has a WERR of less thanabout
 2. 5. A method according to claim 2, in which: the step of heatingsaid substrate in an ambient containing ) O2 is performed for anadjustment time such that the WERR of the final material is madesubstantially equal to a design value.
 6. A method according to claim 3,in which: the step of heating said substrate in an ambient containing O2is performed for an adjustment time such that the WERR of the finalmaterial is made substantially equal to a design value.
 7. A methodaccording to claim 4, in which: the step of heating said substrate in anambient containing O2 is performed for an adjustment time such that theWERR of the final material is made substantially equal to a designvalue.
 8. A method according to claim 1, in which: the trench has anaspect ratio of greater than 6; the trench dielectric material isplanarized by CMP after the step of annealing in an O2 ambient; and ananneal in an ambient containing water vapor is performed after the stepof planarizing for a time sufficient to convert Si—N bonds to Si—O bondsin trench dielectric material at the bottom of the trench.
 9. A methodaccording to claim 8, in which the time of the stress conversion stepand the time of the anneal step are related such that the thermal budgetof the thermally sensitive component is not exceeded.
 10. A methodaccording to claim 8, in which: said step of stress conversion and saidstep of annealing are related such that the resulting material hascompressive stress in the range of 0.1 to 2 Gdynes/cm2 and has a WERR ofless than about
 2. 11. A method according to claim 9, in which: saidstep of stress conversion and said step of annealing are related suchthat the resulting material has compressive stress in the range of 0.1to 2 Gdynes/cm2 and has a WERR of less than about
 2. 12. A methodaccording to claim 9, in which: the step of heating said substrate in anambient containing O2 is performed for an adjustment time such that theWERR of the final material is made substantially equal to a designvalue.
 13. A method according to claim 10, in which: the step of heatingsaid substrate in an ambient containing O2 is performed for anadjustment time such that the WERR of the final material is madesubstantially equal to a design value.
 14. A method according to claim11, in which: the step of heating said substrate in an ambientcontaining O2 is performed for an adjustment time such that the WERR ofthe final material is made substantially equal to a design value.
 15. Amethod of forming an integrated circuit containing a set of circuitelements and a set of isolation trenches comprising the steps of:providing a silicon substrate; etching said set of trenches in saidsilicon substrate; filling said set of trenches with a spin on trenchdielectric material containing silazane; heating said substrate at atemperature of less than about 450 deg C.; converting the stress in saidtrench dielectric material from tensile stress to compressive stress byheating in an ambient containing H2O at a temperature between about 450deg C. and about 900 deg C.; annealing said substrate by heating in anambient containing O2 at a temperature above 800 deg C.; and completingsaid integrated circuit.
 16. A method according to claim 15, in which:said step of stress conversion and said step of annealing are relatedsuch that the resulting material has compressive stress in the range of0.1+2 Gdynes/cm2 and has a WERR of less than about
 2. 17. A methodaccording to claim 16, in which: the step of heating said substrate inan ambient containing O2 is performed for an adjustment time such thatthe WERR of the final material is no greater than a design value.
 18. Amethod according to claim 17, in which: the step of heating saidsubstrate in an ambient containing O2 is performed for an adjustmenttime such that the WERR of the final material is made substantiallyequal to a design value.
 19. A method of forming an integrated circuitcontaining a set of thermally sensitive vertical transistor DRAM cellshaving a thermal budget associated therewith and a set of isolationtrenches, comprising the steps of: providing a silicon substrate;forming at least one vertical transistor DRAM cell having a thermalbudget prior to forming the isolation structure; etching said set oftrenches in said silicon substrate; filling said set of trenches with aspin on trench dielectric material containing silazane; heating saidsubstrate at a temperature of less than about 450 deg C.; converting thestress in said trench dielectric material from tensile stress tocompressive stress by heating in an ambient containing H2O at atemperature between about 450 deg C. and about 900 deg C.; annealingsaid substrate by heating in an ambient containing O2 at a temperatureabove 800 deg C.; and completing said integrated circuit.
 20. A methodaccording to claim 19, in which the time of the stress conversion stepand the time of the anneal step are related such that the thermal budgetof the vertical transistor DRAM cell is not exceeded.
 21. A methodaccording to claim 19, in which: said step of stress conversion and saidstep of annealing are related such that the resulting material hascompressive stress in the range of 0.1 to 2 Gdynes/cm2 and has a WERR ofless than about
 2. 22. A method according to claim 20, in which: saidstep of stress conversion and said step of annealing are related suchthat the resulting material has compressive stress in the range of 0.1to 2 Gdynes/cm2 and has a WERR of less than about
 2. 23. A methodaccording to claim 20, in which: the step of heating said substrate inan ambient containing O2 is performed for an adjustment time such thatthe WERR of the final material is made substantially equal to a designvalue.
 24. A method according to claim 21, in which: the step of heatingsaid substrate in an ambient containing O2 is performed for anadjustment time such that the WERR of the final material is madesubstantially equal to a design value.
 25. A method according to claim22, in which: the step of heating said substrate in an ambientcontaining O2 is performed for an adjustment time such that the WERR ofthe final material is made substantially equal to a design value.
 26. Anintegrated circuit containing a set of thermally sensitive circuitelements having a thermal budget associated therewith and a set ofisolation trenches in a silicon substrate, in which: said set oftrenches have an aspect ratio of at least four and have been filled witha spin on trench dielectric material containing silazane; said substratehas been heated at a temperature of less than about 450 deg C.; thestress in said trench dielectric material is compressive stress that wasconverted from tensile stress to compressive stress by heating in anambient containing H2O at a temperature between about 450 deg C. andabout 900 deg C.; and said substrate has been annealed by heating in anambient containing O2 at a temperature above 800 deg C. until Si—N bondsat the bottom of said trench are substantially converted to Si—O bonds,in which the time of the stress conversion step and the time of theanneal step are related such that the thermal budget of the thermallysensitive component is not exceeded; and said step of stress conversionand said step of annealing are related such that the resulting materialhas compressive stress in the range of 0.1 to 2 Gdynes/cm2, whereby theoperation of transistors adjacent to said set of trenches is notaffected and has a WERR of less than about
 2. 27. A circuit according toclaim 26, in which the time of the stress conversion step and the timeof the anneal step were related such that the thermal budget of thethermally sensitive component was not exceeded.
 28. A circuit accordingto claim 26, in which: said step of stress conversion and said step ofannealing were related such that the resulting material has compressivestress in the range of 0.1 to 2 Gdynes/cm2 and has a WERR of less thanabout
 2. 29. A circuit according to claim 26, in which: a subset ofisolation trenches surround transistor areas containing a transistor;and the time and temperature of the stress conversion step is such thatthe stress in the dielectric trench material is not greater than adesign limit value.
 30. A circuit according to claim 29, in which: thetime and temperature of the stress conversion step is such that thestress in the dielectric trench material is substantially equal to adesign value.
 31. A circuit according to claim 26, in which: the timeand temperature of the stress conversion step and the annealing stepsare such that the stress in the dielectric trench material issubstantially equal to that of oxide deposited by the HDP technique. 32.A circuit according to claim 29, in which: the time and temperature ofthe stress conversion step and the annealing steps are such that thestress in the dielectric trench material is substantially equal to thatof oxide deposited by the HDP technique.